I'm Subrata Banik, having 9+years of experience in BIOS domain. In early 2009 I started my career with American Megatrends (AMI) and widely worked on ARM and IA architecture. Later in 2012 I became part of Intel. Initial few years I worked as UEFI BIOS engineer enabling Windows Tablet platforms, which provided me the opportunity to work with numerous ODM/OEM and IBVs. Later, became a part of Intel Coreboot team exclusively working on Chrome projects. Apart from Intel SoC and platform bring-ups, nowadays I'm primarily focusing on improving IA-Coreboot infrastructure and smoother adaptation of FSP using Coreboot.
coreboot is an extended firmware platform that delivers a lightning fast and secure boot experience on modern computers and embedded systems. The fact that BIOS or Intel firmware touches many restricted register settings which are not exposed to the external world is one of the major challenges for coreboot and that is being addressed by FSP (firmware support package) like binary blob solutions.
Any coreboot project can be split into three parts
• SoC – This section contains all components/IP initialization code.
• Mainboard – OxM boards, build based on underlying SoC support.
• FSP – Intel Firmware Support package to abstract all restricted soc registers from open source world and kept inside a binary blob.
This paper will explain how the open source community can use FSP 2.0 to create their mainboard based ports based on a supported SoC.