Adaptation of AMD Reference Firmware to coreboot© Using FSP 2.0
Recent generations of AMD processors implemented in coreboot have firmware based on AMD Generic Encapsulated Software Architecture (AGESA™) version 5.0, also known as Architecture 2008. AGESA v5 was fully compatible with legacy BIOS as well as UEFI, and so it was easily adapted to coreboot using either sanitized open-source versions of the code or a pre-compiled binary. The newer processors with pre-compiled binaries were supported by an integration specification commonly known as BinaryPI.
With the introduction of the “Zen” core, AMD introduced AGESA Version 9. AGESA v9 was designed to optimize building and executing UEFI BIOS. As part of that optimization, support for legacy BIOS was eliminated. This ended compatibility with the previous BinaryPI interface.
In addition, AMD made a number of other changes in hardware which challenge many of the assumptions built into traditional coreboot flow. The largest of these differences being that memory training is completed by an auxiliary processor core before the x86 core is released from reset. This eliminates many of the pre-memory execution constraints assumed in coreboot flow. However, it does not satisfy all of the requirements of initialization normally dealt with during bootblock, vboot and romstage.
A project was undertaken to adapt AGESA v9 to coreboot using the model of Intel® Firmware Support Package 2.0 (FSP). The FSP provided a basic method to support UEFI firmware execution within a coreboot host firmware. While this addresses many of the issues with execution, FSP is also built on assumptions about pre-memory execution and order of operations for Intel processors which are not true for others.
This paper will discuss the solution developed for an AMD Family 17h and associated Mandolin reference board which incorporates Tianocore EDK2 and AGESA v9 into the broadly recognized constructs of coreboot and FSP.