ronald g. minnich
Ron Minnich invented coreboot. More recently, he started the LinuxBoot project (linuxboot.org), which uses another of his projects, u-root (u-root.org). His most recent project is oreboot, i.e., coreboot without 'c'; oreboot is written in Rust.
How Min Platform led to Max coreboot; a case study
LinuxBoot is now widely deployed, by many companies, on millions of systems, in data centers around the world. LinuxBoot was started, in 2017, by intent, as a UEFI project. To put it more strongly, in the beginning, we explicitly rejected coreboot integration as a primary, secondary, or even tertiary goal.
The entire thrust of LinuxBoot was to greatly reduce the size of UEFI, and hence the large attack surface UEFI represented, and replace most of UEFI with Linux. But we never intended to replace all of UEFI: we had no desire to re-argue the UEFI vs. coreboot debate, and, indeed, saw no prospect of ever resuming use of coreboot on x86 servers.
The world is full of surprises. Once companies began to realize how little of UEFI they needed, they began to ask how to remove it completely. As chance would have it, Meta and Intel had started the Sapphire Rapids (SPR) server chipset effort for coreboot. Companies needed coreboot on a modern server chipset; the SPR effort showed a way to get it. The final piece was the structuring of a multi-party NDA to allow joint collaboration.
In this talk, I'll discuss how a project designed for minimized UEFI platforms has now come to include coreboot, and what may come in the future, as more companies join in multi-party NDA efforts on even newer chipsets.
oreboot 2022 status report - on to RISC-V
This year we pivoted the oreboot project, a downstream fork of coreboot
written entirely in Rust, to focus on RISC-V platforms, including the first
version of Beagle-V. We have focused our energies on platforms we can control from power-on reset, with no binary blobs.
Over the last year, the Allwinner D1 SoC, which offers a Linux-capable 64bit
XuanTie C906 RISC-V core and is found on many boards, has been fully ported,
including DRAM init. In addition, we picked up the work on the JH7100 SoC again
that was found on the BeagleV Starlight SBC, because it is also on the StarFive
VisionFive board, which has been provided to us by RISC-V International for the
developer support program.
In this talk, we present challenges we faced during
the development, including writing DRAM code from C code, not chipset documentation;
how we are taking advantage of the rapid growth of "bare metal" support in the Rust ecosystem and
how it has impacted our code, in ways large and small; and how the project is growing as new members
Finally, we summarize the current status of the oreboot project.