Memory-Mapped FPGA Peripherals on Zephyr: FMC and QSPI Approaches

Sahaj Sarup

High-speed interfaces are rare on MCUs, and cost-effective FPGAs often come with limited LUTs, leaving developers caught between slow protocols like I2C/UART and the complexity of rolling a custom SPI protocol from scratch.

This talk explores a cleaner alternative: interfacing an FPGA as a memory-mapped device with an MCU running Zephyr, and extending that interface to expose gateware peripherals inside the FPGA. We'll cover two approaches, direct memory mapping over STM32's FMC bus, and a QSPI-based approach treating the FPGA as a SPI memory device, comparing their trade offs in speed, complexity, and flexibility.

Key takeaways:

  1. Writing Devicetree for Memory mapped FPGAs using STM32’s FMC Bus.
  2. Writing Devicetree for Memory Mapped FPGAs using Generic serialised SPI/QSPI interfaces.
  3. Using the FPGA as MMU for external memory like HyperRAM.
  4. Interfacing gateware peripherals in the FPGA from MCU running Zephyr
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